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- W1968597908 abstract "In this paper, we present a circuit technique that supports a super-drowsy mode with a single-V DD . In addition, we perform a detailed working set analysis for various cache line update policies for placing lines in a drowsy state. The analysis presents a policy for an instruction cache and shows it is as good as or better than more complex schemes proposed in the past. Furthermore, as an alternative to using high-threshold devices to reduce the bitline leakage through access transistors in drowsy caches, we propose a gated bitline precharge technique. A single threshold process is now sufficient. The gated precharge employs a simple but effective predictor that almost completely hides any performance loss incurred by the transitions between sub-banks. A 64-entry predictor with 3 bits per entry reduces the run-time increase by 78%, which is as effective as previous proposals that used content addressable predictors with 40 bits per entry. Overall, the combination of the proposed techniques reduces the leakage power by 72% with negligible (0.4%) run-time increase." @default.
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- W1968597908 date "2004-08-09" @default.
- W1968597908 modified "2023-10-10" @default.
- W1968597908 title "Single-v <sub>DD</sub> and single-v <sub>T</sub> super-drowsy techniques for low-leakage high-performance instruction caches" @default.
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- W1968597908 doi "https://doi.org/10.1145/1013235.1013254" @default.
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