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- W1969284342 abstract "High-κ dielectric stacks have been used to replace the conventional SiO <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> -based dielectric stacks in Flash memory cells in the 20 nm technology generation. The electron trap density in high-κ layers is orders of magnitude higher than that in SiO <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> , which introduces fast transient trapping/detrapping and affects the program/erase, retention and endurance of memory cells. Several fast pulse techniques have been developed to characterize electron traps throughout the dielectric stack, including 2-pulse and multi-pulse C-V and I-V techniques. These techniques are compared in this work and electron trapping in the high-κ stacks and its impact on memory cell performances are evaluated using these techniques." @default.
- W1969284342 created "2016-06-24" @default.
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- W1969284342 date "2012-10-01" @default.
- W1969284342 modified "2023-09-25" @default.
- W1969284342 title "Characterisation of electron traps in high-k dielectric stacks for Flash memory applications using fast pulse techniques" @default.
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- W1969284342 doi "https://doi.org/10.1109/icsict.2012.6466698" @default.
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