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- W1970064013 abstract "A novel high-performance bipolar-CMOS (complementary metal oxide semiconductor) merged technology for a 1-Mb DRAM (dynamic random access memory) is proposed. A memory cell having a twenty-times-higher soft-error immunity (as compared to the conventional device) in its bit-line mode and a bipolar transistor having a high-drive ability (f/sub T/=5.2 GHz at I/sub c/=1.2 mA) can be realized. The fabrication process is fully compatible with the conventional CMOS DRAM and involves only three additional masking steps. An experimental 1-Mb BiCMOS (bipolar CMOS) DRAM was fabricated using this technology, with a typical access time of 32 ns.< <ETX xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>></ETX>" @default.
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- W1970064013 date "1989-04-01" @default.
- W1970064013 modified "2023-09-25" @default.
- W1970064013 title "Bipolar CMOS-merged technology for a high-speed 1-Mbit DRAM" @default.
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- W1970064013 doi "https://doi.org/10.1109/16.22475" @default.
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