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• W1971175520 abstract "We describe asynchronous circuits that can relay spikes between multiple chips in a grid. These circuits interface with an on-chip SRAM to implement programmable connectivity among chips. We introduce a packet format that is compatible with updating the SRAM. From a high level specification, we synthesized and fabricated these circuits in an area of 0.206mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> in 0.18- <i xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>μ</i> m CMOS technology. Test results that measure performance and demonstrate correct function on first silicon are presented." @default.
• W1971175520 created "2016-06-24" @default.
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• W1971175520 date "2006-08-01" @default.
• W1971175520 modified "2023-10-17" @default.
• W1971175520 title "Programmable Connections in Neuromorphic Grids" @default.
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• W1971175520 doi "https://doi.org/10.1109/mwscas.2006.382000" @default.
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