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- W1972376710 abstract "Nonbinary low-density parity-check (NB-LDPC) codes outperform their binary counterparts in some cases, but their high decoding complexity is a significant hurdle to their applications. In this paper, we propose a decoding algorithm with reduced computational complexities and smaller memory requirements for NB-LDPC codes. First, a simplified algorithm is proposed to reduce the computational complexity of variable node processing. To reduce the memory requirements, existing NB-LDPC decoders often truncate the message vectors to a limited number n m of values. However, the memory requirements of these decoders remain high when the field size is large. In this paper, an improved trellis-based check node processing algorithm is proposed to significantly reduce the memory requirement. The number of elements in a variable-to-check message is reduced to n v (n v <; n m). The sorted log likelihood ratio (LLR) vector of a check-to-variable (c-to-v) message is approximated using a piecewise linear function. For each a priori message, most of the LLRs are approximated with a linear function. Two low complexity LLR generation units (LGUs) are proposed to compute LLR vectors for c-to-v messages. A fully parallel NB-LDPC decoder over GF(256) is implemented with 28-nm CMOS technology. The decoder over GF(256) achieves a throughput of 546 Mb/s and an energy efficiency of 0.178 nJ/b/iter." @default.
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- W1972376710 date "2014-12-01" @default.
- W1972376710 modified "2023-10-14" @default.
- W1972376710 title "An Efficient Fully Parallel Decoder Architecture for Nonbinary LDPC Codes" @default.
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- W1972376710 doi "https://doi.org/10.1109/tvlsi.2013.2293224" @default.
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