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- W1972408170 abstract "Jet Propulsion Laboratory has developed an innovative Grayscale Optical Correlator (GOC) architecture using apair of Digital Light Processor Spatial Light Modulator (DLP SLM) as the input and filter devices and a CMOSsensor for correlation output detection [1-5]. In order to achieve ultra high-speed Automatic Target Recognition(ATR), we have developed custom Electronic Interfaces to maximize the system data throughput rate for both theDLP and CMOS. The high-performance Electronic Interface System (EIS) is capable of achieving sustained 1000frames per second (fps) at 1920x1024 data frame size. In this paper, we will first overview the new GOCarchitecture. We will the depict the detailed design of the EIS for the DLP SLM and CMOS. The innovation ofJPL’s high-performance digital/optical ATR system is in its implementation of a high-speed, high-resolution DLPdisplay, and a high-speed CMOS camera sensor with an advanced I/O interface and high-speed parallel on-boardprocessing capability." @default.
- W1972408170 created "2016-06-24" @default.
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- W1972408170 date "2013-04-29" @default.
- W1972408170 modified "2023-10-03" @default.
- W1972408170 title "High-speed optical correlator with custom electronics interface design" @default.
- W1972408170 cites W2000513147 @default.
- W1972408170 doi "https://doi.org/10.1117/12.2018262" @default.
- W1972408170 hasPublicationYear "2013" @default.
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