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- W1973454118 abstract "We present an effective recursive algorithm for circuit clustering for delay and area minimization, which is applicable to FPGAs. At the highest level of clustering, the circuit is clustered using a modified single-level clustering algorithm. A cluster to netlist transformation technique is proposed, which converts each cluster into a new subcircuit. The algorithm then continues recursively by clustering the generated subcircuits into further levels of clusters. To reduce the amount of node duplication and the number of clusters at each level of clustering, we propose a node removal algorithm based on the node slack along with a simple cluster-packing algorithm. Experimental results on the two-level clustering problem using Quartus Design System from Altera show that our algorithm achieves, on average, 7.3% more delay reduction when compared to the latest published work on the problem. Also total FPGA compile time reported by Quartus is reduced by 36%." @default.
- W1973454118 created "2016-06-24" @default.
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- W1973454118 date "2003-02-23" @default.
- W1973454118 modified "2023-09-27" @default.
- W1973454118 title "Recursive circuit clustering for minimum delay and area" @default.
- W1973454118 doi "https://doi.org/10.1145/611817.611865" @default.
- W1973454118 hasPublicationYear "2003" @default.
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