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W1976522275 abstract "This paper describes a 64% locking-range type-I LC PLL architecture with a small loop filter area. By employing a dual-path LC VCO with a boosted open-loop gain at dc, a reference spur or a static phase error problem with a large frequency offset in the type-I PLL is alleviated. The prototype PLL is implemented in 0.13μm CMOS, achieving 2.74-to-5.37GHz locking range with <;-50dBc reference spur over active locking range." @default.
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W1976522275 date "2012-06-01" @default.
W1976522275 modified "2023-09-27" @default.
W1976522275 title "A 2.74–5.37GHz boosted-gain type-I PLL with &#60;15% loop filter area" @default.
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W1976522275 doi "https://doi.org/10.1109/rfic.2012.6242259" @default.
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