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- W1976945405 abstract "Design of a resolution/sampling-rate/power-optimized analog-to-digital converter (ADC) in a foundry 0.25 /spl mu/m SiGe BiCMOS for digital communications is presented. It is based on a combined four-stage multi-bit pipelined, subranging and interpolating architecture with novel digital correction technique. The expanded subranging structure along with the proposed multiple MDAC (multiplying DAC) and relative comparison method used in sub ADC simplifies the 2/sup nd/ and 3/sup rd/ stages. The ADC features 12 bit resolution, 200 MHz sampling rate, differential nonlinearity (DNL) of /spl plusmn/0.6 LSB, integral nonlinearity (INL) of /spl plusmn/1.1 LSB, power dissipation of 380 mW and a die size of 6 mm/sup 2/." @default.
- W1976945405 created "2016-06-24" @default.
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- W1976945405 date "2005-07-27" @default.
- W1976945405 modified "2023-10-15" @default.
- W1976945405 title "A 12bits/200MHz Resolution/Sampling/Power-Optimized ADC In 0.25μ SiGe BiCMOS" @default.
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- W1976945405 doi "https://doi.org/10.1109/iscas.2005.1466050" @default.
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