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- W1977163765 abstract "The erase voltage impact on the 0.18 μm triple self-aligned split-gate flash endurance is studied. An optimized erase voltage is necessary in order to achieve the best endurance. A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop, which is induced by tunnel oxide charge trapping during program/erase cycling. A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping. A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance." @default.
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- W1977163765 date "2010-06-01" @default.
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- W1977163765 title "Erase voltage impact on 0.18 μm triple self-aligned split-gate flash memory endurance" @default.
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