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- W1980872829 abstract "Dynamic Injection MNOS (DIMNOS) memory devices feature high-speed writing, 5-V drain voltage, and MNOS backup one-transistor-type dynamic RAM's. They are written on MNOS, like conventional one-transistor-type dynamic RAM's, when high writing voltage is applied to the MNOS gate. In experiments with DIMNOS, the threshold-voltage shift ( <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>Delta V_{th}</tex> ) of MNOS in the writing mode does not depend very much on temperature; <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>Delta V_{th}</tex> in the write-inhibited mode depends hardly at all on temperature; and <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>Delta V_{th}</tex> in the write-inhibited mode decreases under the condition that the product of the number of attempts and pulsewidth is constant when he pulsewidth is longer than 10 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>-4</sup> s. The proposed model in the write-inhibited mode means that weak avalanche occurs due to field concentration between the control transistor and MNOS memory region. As a result, hot electrons are injected between the ultrathin SiO <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</inf> and Si <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>3</inf> N <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>4</inf> films of MNOS. This model is supported by the above mentioned experimental results in the write-inhibited mode." @default.
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- W1980872829 date "1981-07-01" @default.
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- W1980872829 title "A model of write-inhibition in dynamic injection MNOS" @default.
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- W1980872829 doi "https://doi.org/10.1109/t-ed.1981.20441" @default.
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