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• W1980967110 abstract "The increasing usage of flash memory in mobile applications is pushing the scaling limit of Flash memory technology. This paper presents a systematic scaling methodology, architecture, optimization strategy, and performance of sub-90 nm split-gate flash memory cells. The device simulation results show that the split-gate cells can be scaled to 90 nm node and below using shallow source/drain junctions and a highly localized source-halo in conjunction with channel engineering. Using properly optimized technology parameters, sub-90 nm cells with tolerable leakage current and efficient time-to-program and time-to-erase can be achieved" @default.
• W1980967110 created "2016-06-24" @default.
• W1980967110 creator A5070458497 @default.
• W1980967110 date "2006-01-01" @default.
• W1980967110 modified "2023-09-26" @default.
• W1980967110 title "Scaling considerations for sub-90 nm split-gate flash memory cells" @default.
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• W1980967110 doi "https://doi.org/10.1109/icsict.2006.306442" @default.
• W1980967110 hasPublicationYear "2006" @default.
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