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- W1981184870 abstract "N-channel normally-off InP MISFETs for high-gain and high-speed application have been developed, using the following fabrication techniques: (1)Sulphur diffusion process into p- and semi-insulating InP wafers for low resistive source and drain of the n-channel FET. (2)Al <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</inf> O <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>3</inf> CVD method onto the InP substrate. (3)n-channel formation on the semi-insulating InP substrate surface. (4)A pseudo self-alignment technique for eliminating gate-drain and gate-source parasitic capacitances. Conductance and drift properties have been studied together with MIS diode capacitance measurement and AES analysis." @default.
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- W1981184870 date "1980-01-01" @default.
- W1981184870 modified "2023-09-23" @default.
- W1981184870 title "Fabrication and performance of InP MISFET" @default.
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- W1981184870 doi "https://doi.org/10.1109/iedm.1980.189862" @default.
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