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- W1983142009 abstract "A new topology in PLL architecture dual-mode KVCO (DMK) to reduce in-band noise and reference spurs is presented. The DMK PLL also adopts the technique to shrink the spurs by modulating the control voltage. The prototype DMK PLL is implemented in a 65 nm CMOS and shows about 3 ps RMS jitter, phase noise of −107 and −109 dBc/Hz at 100 kHz, 1 MHz offset frequency and reference spur of 68.5 dBc." @default.
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- W1983142009 date "2010-01-01" @default.
- W1983142009 modified "2023-09-26" @default.
- W1983142009 title "Dual-mode VCO gain topology for reducing in-band noise and reference spur of PLL in 65 nm CMOS" @default.
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- W1983142009 doi "https://doi.org/10.1049/el.2010.3553" @default.
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