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- W1983237066 abstract "Unlike general-purpose programs, it is important to reduce the worst-case performance rather than the average-case performance for real-time systems. In this paper, based on a dual-core processor with a shared L2 cache, we propose a code positioning scheme that can reduce the worst-case execution time (WCET) for real-time threads by minimizing both the intra-thread and inter-thread instruction cache misses. Our experiments indicate that the proposed hybrid code positioning approach can effectively reduce the worst-case performance for real-time threads running on this dual-core processor." @default.
- W1983237066 created "2016-06-24" @default.
- W1983237066 creator A5021728589 @default.
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- W1983237066 date "2010-03-13" @default.
- W1983237066 modified "2023-09-23" @default.
- W1983237066 title "Multicore-aware hybrid code positioning to reduce worst-case execution time" @default.
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- W1983237066 doi "https://doi.org/10.1145/1739025.1739029" @default.
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