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• W1983299256 abstract "In this paper, we study the implements a data rate can be adjusted, m series can be equipped with pseudo-random series of sequence generator. This design in the basis of linear feedback shift register, through the linear feedback function to produce mould the longest m sequence. In order to carry on it, we use the hardware description language VHDL, take advantage of the FPGA reconfigurability and flexibility, using Quartus II 8.0 for the integrated wiring, and give the Model simulation waveforms. For the sake of verifying the feasibility of this design, we adapt it to the DE2 board, and with an oscilloscope and other equipment were tested." @default.
• W1983299256 created "2016-06-24" @default.
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• W1983299256 date "2012-02-01" @default.
• W1983299256 modified "2023-09-26" @default.
• W1983299256 title "The Design and Implementation of a Parallel Configurable Paseudorandom Sequence Generator" @default.
• W1983299256 cites W1970708539 @default.
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• W1983299256 doi "https://doi.org/10.4028/www.scientific.net/amr.468-471.1903" @default.
• W1983299256 hasPublicationYear "2012" @default.
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