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• W1983362917 abstract "In this paper, the length scaling of the silicon Double Gate Tunnel Field Effect Transistor (DG Tunnel FET) is studied. It is found that scaling limits are reached sooner by Tunnel FETs with an SiO2 gate dielectric, while those with a high-K dielectric can be scaled further before threshold voltage, and average and point subthreshold swing are affected. It is demonstrated that the scaling of the high-K Tunnel FET is completely different than that of conventional MOS transistors. An outstanding feature of the Tunnel FET switch is that length scaling has a much weaker impact on device characteristics than does gate control (e.g. the use of a high-K dielectric), which primarily dictates the tunneling barrier width and consequently, device conduction. This paper demonstrates that while some improvements are observed, the length scaling does not dramatically affect switch figures of merit such as subthreshold slope, Ion and Ioff down to about 20 nm, and an optimized device design can be extended over a much larger window of sub-micron dimensions, compared to the MOSFET. A discussion of the length dependence of the transconductance, gm, and output conductance, gds of the Tunnel FET is presented for the first time." @default.
• W1983362917 created "2016-06-24" @default.
• W1983362917 creator A5010655246 @default.
• W1983362917 creator A5053654772 @default.
• W1983362917 date "2007-11-01" @default.
• W1983362917 modified "2023-10-16" @default.
• W1983362917 title "Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric" @default.
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• W1983362917 doi "https://doi.org/10.1016/j.sse.2007.09.014" @default.
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