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- W1985148270 abstract "In this paper, we propose a parallel processing architecture, based on two TMS320C44 VME-bus DSP boards, for real time implementation of Cell Averaging and Clutter Map Constant False Alarm Rate (CFAR) detectors, and a data extractor based on a centroidal interpolation of the position of the detected target. The optimal processing speed has been achieved by fully exploiting the capacities of the dasiaC44 processor. The implemented system is well adapted for two dimension radars. The overall processing scheme interconnections and the real time implementation results are presented and discussed." @default.
- W1985148270 created "2016-06-24" @default.
- W1985148270 creator A5083282525 @default.
- W1985148270 date "2008-05-01" @default.
- W1985148270 modified "2023-09-25" @default.
- W1985148270 title "Design and real time implementation of a radar data extractor" @default.
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- W1985148270 doi "https://doi.org/10.1109/irs.2008.4585783" @default.
- W1985148270 hasPublicationYear "2008" @default.
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