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- W1985280372 abstract "This paper presents a simple circuital technique to design efficient pulse triggered flip-flops. The proposed approach aims at considerably alleviating the detrimental effects of current contention mechanisms, occurring at critical switching nodes during an output switching. In this way, both latency and power consumption are reduced. The proposed approach is assessed by means of simulations in 90-nm ST commercial CMOS technology. When applied to some recently proposed implicit pulse triggered flip-flop architectures, the suggested design strategy, allows speed to be improved up to 13% and power-delay-product to be lowered down to 14%. Moreover, also the process variation tolerance is considerably improved." @default.
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- W1985280372 date "2014-02-01" @default.
- W1985280372 modified "2023-10-18" @default.
- W1985280372 title "Improving speed and power characteristics of pulse-triggered flip-flops" @default.
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- W1985280372 doi "https://doi.org/10.1109/lascas.2014.6820287" @default.
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