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• W1985687118 abstract "This paper describes the fabrication of pentacene-based thin film transistors (TFTs) with ultrathin (4.5nm) SiO2 and SiON gate dielectric layers for low-voltage operations. The device with the SiON gate dielectric layer operated at gate voltages lower than −3.0V, showing a threshold voltage of −0.45V, which was lower than the threshold voltage of the SiO2 device (−2.5V). The electronic structures of the interface between the pentacene and dielectric layers were investigated by in situ ultraviolet photoelectron spectroscopy (UPS) and x-ray photoelectron spectroscopy (XPS) to determine the reason for the lower operating voltage. The UPS and XPS results demonstrated that the interface dipole modified the potential of the dielectric layer, explaining the lower operating voltage. The electronic structure allowed for band bending at the interface, resulting in complete energy level diagrams for pentacene on SiO2 and SiON. The shifts in the threshold and turn-on voltages were explained by the energy level diagrams." @default.
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• W1985687118 date "2007-09-15" @default.
• W1985687118 modified "2023-10-06" @default.
• W1985687118 title "Electronic structure of pentacene/ultrathin gate dielectric interfaces for low-voltage organic thin film transistors" @default.
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• W1985687118 doi "https://doi.org/10.1063/1.2779264" @default.
• W1985687118 hasPublicationYear "2007" @default.
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