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- W1986738882 abstract "Inherent in the structure of bulk CMOS integrated circuits are four-layer parasitic paths that can become activated into a low impedance, high-current state, i.e., latch-up. Activation can be accomplished by photocurrents generated by ionizing radiation or by terminal over-voltage spikes. As loss of functionality or device destruction can result, latch-up is undesirable. This paper describes a method of latchup prevention by the use of n on n+ starting material. A graphical analysis is presented that aids in the understanding of the latch-up mechanism and provides insight into the elimination of that state. Experimental data in support of the model is presented." @default.
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- W1986738882 date "1980-01-01" @default.
- W1986738882 modified "2023-09-24" @default.
- W1986738882 title "Latch-Up Elimination in Bulk CMOS LSI Circuits" @default.
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- W1986738882 doi "https://doi.org/10.1109/tns.1980.4331097" @default.
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