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- W1988783304 abstract "For modern high speed DAC, receiving data reliably from FPGA is a big challenge, data-independent skew is the major problem. usually system employ data clock while transmitting LVDS data from FPGA. then LVDS data is latched by delayed data clock which generated by DLL in chip. Because DLL has a negative feedback loop, system suffer small effect of PVT variations, robustness is guaranteed. The receiving circuits were implemented in a all-digital 0.18μm CMOS technology ,occupies 0.7 mm 2 of area. It operates in the frequency range of 20 MHz~600 MHz." @default.
- W1988783304 created "2016-06-24" @default.
- W1988783304 creator A5008824959 @default.
- W1988783304 date "2013-08-01" @default.
- W1988783304 modified "2023-10-03" @default.
- W1988783304 title "DLL-Based Receiver for High Speed Data Transmission" @default.
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- W1988783304 doi "https://doi.org/10.4028/www.scientific.net/amr.753-755.2471" @default.
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