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- W1989222640 abstract "While existing architectures like x86 and SPARC provide strong hardware memory consistency models, such as TSO, programming language memory models are more relaxed. This divide nullifies the usefulness of providing strong hardware memory models, since languages and compilers provide a weaker guarantee. Moreover, current shared memory systems implement complex cache coherence protocols which add to the complexity. This work proposes a microarchitecture, called Viser, that ensures strong semantics---serializability of synchronization-free regions (SFRs)---in the absence of region conflicts even for racy program executions. Given an execution, Viser either reports a serializability violation or guarantees SFR-serializability, in effect providing the same guarantees provided by languages such as C++ and Java for data-race-free programs only. Viser's design also allows for greatly simplifying existing cache coherence protocols, without requiring any assumptions about language-level properties such as data-race-freedom." @default.
- W1989222640 created "2016-06-24" @default.
- W1989222640 creator A5089244894 @default.
- W1989222640 date "2015-10-25" @default.
- W1989222640 modified "2023-09-25" @default.
- W1989222640 title "Viser: providing serializability in hardware with simplified cache coherence" @default.
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- W1989222640 doi "https://doi.org/10.1145/2814189.2815375" @default.
- W1989222640 hasPublicationYear "2015" @default.
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