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- W1989759022 abstract "In a scan-based test architecture, the scan power and and test data volume can be reduced by utilizing a double tree scan (DTS) architecture. This paper presents a novel hardware implementation of the DTS architecture and compares the hardware overhead with the conventional scan architecture. The implementation proposed utilizes a clock structure which greatly decreases the number of clocked flip-flops and thereby reduces power consumption. A test chip is designed and fabricated in a 0.5 μm CMOS technology to verify the power saving properties of the architecture." @default.
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- W1989759022 date "2010-05-01" @default.
- W1989759022 modified "2023-10-16" @default.
- W1989759022 title "Hardware implementation of the double-tree scan architecture" @default.
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- W1989759022 doi "https://doi.org/10.1109/iscas.2010.5537687" @default.
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