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- W1989785283 abstract "A 1-V 2.4 GHz low-spur phase-locked loop (PLL) fractional-N frequency synthesizer with a subsampling charge pump and a randomly selected phase frequency detector is implemented by TSMC 0.18-μm CMOS process. The proposed frequency synthesizer randomizes the periodic ripples on the controlled voltage from the voltage-controlled oscillator to reduce the reference spur at the output of the PLL. A random clock generator is used to perform this random selection control. At 1-V supply voltage, measured results of the proposed prototype achieve the tuning range of 2.235–2.579 GHz, corresponding to 14.3%, a phase noise of −113.17 dBc/Hz at 1 MHz offset frequency from 2.41 GHz, an output power of −4.534 dBm with a reference spur of −70.4 dBc and a power consumption of 9 mW. Including pads, the chip area only occupies 0.695 (0.819 × 0.849) mm2. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:61–66, 2015" @default.
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- W1989785283 date "2014-11-18" @default.
- W1989785283 modified "2023-09-26" @default.
- W1989785283 title "The 1-V 2.4 GHz low-spur fractional-N frequency synthesizer chip design with exploiting randomly selected PFD and sub-sampling charge pump technology" @default.
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- W1989785283 doi "https://doi.org/10.1002/mop.28778" @default.
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