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- W1989968589 abstract "Scalable Logic Gate Non-Volatile Memory (SLGNVM) devices fabricated with standard CMOS logic process have been demonstrated with 110 nm, 55 nm, and 40 nm nodes. The cell sizes for the NOR flash array complied with the process design rules of the CMOS logic nodes are 0.5424 μm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> , 0.2287 μm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> , and 0.1095 μm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> , respectively. The SLGNVM devices have 3V ~ 5V program/erase windows with good data retention and endurance properties. The arrays of SLGNVM devices are suitable for embedded EEPROM and flash in digital circuitries, and for the new applications of non-volatile-SRAM (nvSRAM), Non-Volatile-Register (NVR), and non-volatile FPGA (nvFPGA)." @default.
- W1989968589 created "2016-06-24" @default.
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- W1989968589 date "2014-10-01" @default.
- W1989968589 modified "2023-10-12" @default.
- W1989968589 title "Scalable Logic Gate Non-Volatile Memory" @default.
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- W1989968589 doi "https://doi.org/10.1109/nvmts.2014.7060846" @default.
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