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- W1989974210 abstract "This paper presents a systolic bit-parallel multiplier with flexible latency and complexity over GF(2m) using polynomial basis. Via the employment of shift register array and pipeline strategy, the multiplier designed in this paper is able to work pipelining parallel with smaller critical path. A cell which could reach the function of reducing the input operand’s degree by one and add the results of different degrees together is created in this paper. The systolic bit-parallel multiplier can be made of several such cells. Several multipliers which have different latencies and complexities with pipeline strategy are created with further discuss, the comprehensive performances of these designs are estimated with the parameter of area-time. At the end of the page, we compare the systolic bit-parallel multiplier of this paper with a certain number of typical designs these years, the result shows that the design in this paper obtains a comprehensive performance improvement by 70%, 27% and 31%." @default.
- W1989974210 created "2016-06-24" @default.
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- W1989974210 date "2012-01-01" @default.
- W1989974210 modified "2023-09-23" @default.
- W1989974210 title "A Systolic Bit-Parallel Multiplier with Flexible Latency and Complexity over GF(2m) Using Polynomial Basis" @default.
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- W1989974210 doi "https://doi.org/10.4028/www.scientific.net/amr.457-458.848" @default.
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