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- W1990400900 abstract "Architectural simulations of microprocessors are extremely time-consuming nowadays due to the ever increasing complexity of current applications. In order to get realistic workloads for the architectural simulations, benchmarks need to constructed with huge dynamic instruction counts. For example, SPEC released the CPU2000 benchmark suite containing benchmarks that have a dynamic instruction count of several hundreds of billions of instructions. This is beneficial for real hardware evaluation. However, simulating these workloads is impractical if not impossible if we take into account that many simulation runs are needed in order to evaluate a large number of design points. Trace sampling is often proposed as a practical solution for this problem. In trace sampling, several representative samples are chosen from a real program trace. Since the sampled trace is much shorter than the original trace, a significant speedup is obtained. In this paper, we study how parallel processing can speedup the simulation of the sampled traces even further. Therefore, we propose and evaluate two ways of distributing sampled traces over parallel machines while taking into account the additional overhead due to the cold-start problem associated with trace sampling. We conclude that in many (practical) trace sampling scenarios, 'distributing samples' is more efficient than 'distributing traces'. This information will help researchers and computer designers in speeding up their simulation runs." @default.
- W1990400900 created "2016-06-24" @default.
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- W1990400900 date "2004-03-01" @default.
- W1990400900 modified "2023-10-17" @default.
- W1990400900 title "Efficient simulation of trace samples on parallel machines" @default.
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- W1990400900 doi "https://doi.org/10.1016/j.parco.2004.02.003" @default.
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