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- W1991345923 abstract "This paper describes a one-dimensional compactor which works efficiently on basic VLSI layout. The compactor operates on a tiled layout structure which represents any VLSI layout containing 45° multiple angles. The compaction program performs both pitch minimization and wire length minimization in either X or Y directions. The compactor works quickly and efficiently due to the clever use of the layout structure and graph based Simplex method. The compactor corrects design rule violations and preserves wire widths. It does not yet introduce jogs or compact hierarchically. Results are given for a few CMOS examples." @default.
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- W1991345923 date "1988-06-01" @default.
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- W1991345923 title "An efficient compactor for 45° layout" @default.
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- W1991345923 doi "https://doi.org/10.5555/285730.285794" @default.
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