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- W1991362337 abstract "Supply voltage is one of the dominant factors that determine the timing performance and power consumption of VLSI chips. For digital systems with a single supply voltage, some logic devices typically operate faster or more frequently than necessary, consuming extra power. This motivates the need for multiple-voltage design for an aggressive power optimization as slow operation allows a reduced voltage level. While the past few years have seen some successful examples from behavioral- and logic-level synthesis, physical designers are facing the challenges under such a new design environment. This talk discusses the physical aspects of multiple-voltage design, including the latest approaches to emerging problems such as voltage interface, clock distribution, power/ground network, and place-and-route (for more info, visit the web site at: http://www.vlsi.uwindsor.ca/~cchen). The goal is to enable designers to deal with key issues in implementation of multiple-voltage chips." @default.
- W1991362337 created "2016-06-24" @default.
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- W1991362337 date "2002-04-07" @default.
- W1991362337 modified "2023-09-27" @default.
- W1991362337 title "Physical design with multiple on-chip voltages" @default.
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- W1991362337 doi "https://doi.org/10.1145/505388.505417" @default.
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