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- W1992393033 abstract "In this paper, we present an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264 / MPEG4 Part 10 video coding standard. The hardware design is based on a novel organization of the intra prediction equations. This hardware is designed to be used as part of a complete H.264 video coding system for portable applications. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 90 MHz in a Xilinx Virtex II FPGA. The FPGA implementation can process 27 VGA frames (640x480) per second." @default.
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- W1992393033 date "2007-04-16" @default.
- W1992393033 modified "2023-09-26" @default.
- W1992393033 title "Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm" @default.
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- W1992393033 doi "https://doi.org/10.5555/1266366.1266406" @default.
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