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• W1992496403 abstract "Gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with multiple nanowire channels has better performance compared with planar TFT, such as lower threshold voltage V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>TH</sub> , smaller subthreshold swing (SS), lower minimum current I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>OFF</sub> , higher maximum on/off current ratio I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>ON</sub> /I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>OFF</sub> , and higher mobility. However, each nanowire has three sharp corners to obtain high local electric fields under gate bias stresses, such that GAA TFT inherently suffers from an inevitable reliability problem. The local electric fields accelerate the degradation of V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>TH</sub> and SS. The V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>TH</sub> degradation under negative gate bias stress is related to the released electron trapping in stressed gate oxide during diffusion-controlled electrochemical reaction. For GAA TFT, minimum I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>OFF</sub> and I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>ON</sub> /I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>OFF</sub> ratio still maintain better characteristics due to smaller channel body. Moreover, the obvious retardation in mobility degradation was obtained for GAA TFT because the hydrogen atoms can effectively rearrange the tail states located near the band edge in the channel during gate bias stresses." @default.
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• W1992496403 date "2012-08-01" @default.
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• W1992496403 title "Gate Bias Stresses of Gate-All-Around Poly-Si TFTs With Multiple Nanowire Channels" @default.
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