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- W1992508758 abstract "It is known that a sequential machine is realized by a binary sequential circuit (BSC). In this paper we try to construct a fail-safe BSC realizing a given sequential machine with the additional constraint that its output either takes the correct value or fails from 0 to 1 if the outputs of logic components in BSC, such as AND, OR, NOT gates and DELAY elements, fail asymmetrically from 0 to 1. The word “fail-safe≓ means that the failure 0 → 1 is considered safe while the reverse is not. It is rather easy to construct a fail-safe BSC for a given sequential machine. The main purpose of this paper is to construct a fail-safe BSC with the smallest number of DELAY's. First we construct a positive BSC with the smallest number of DELAY's. A BSC is positive if its logic components are all positive. Positive BSC's are fail-safe but the converse is not true. Then we also construct a fail-safe BSC with the smallest number of DELAY's. We see that the procedure for the latter construction is more complicated than the former." @default.
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- W1992508758 date "1973-02-01" @default.
- W1992508758 modified "2023-10-18" @default.
- W1992508758 title "Fail-safe realization of sequential machines" @default.
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- W1992508758 doi "https://doi.org/10.1016/s0019-9958(73)90468-3" @default.
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