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• W1993099545 abstract "The DRAM main memory system in modern servers is largely homogeneous. In recent years, DRAM manufacturers have produced chips with vastly differing latency and energy characteristics. This provides the opportunity to build a heterogeneous main memory system where different parts of the address space can yield different latencies and energy per access. The limited prior work in this area has explored smart placement of pages with high activities. In this paper, we propose a novel alternative to exploit DRAM heterogeneity. We observe that the critical word in a cache line can be easily recognized beforehand and placed in a low-latency region of the main memory. Other non-critical words of the cache line can be placed in a low-energy region. We design an architecture that has low complexity and that can accelerate the transfer of the critical word by tens of cycles. For our benchmark suite, we show an average performance improvement of 12.9% and an accompanying memory energy reduction of 15%." @default.
• W1993099545 created "2016-06-24" @default.
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• W1993099545 date "2012-12-01" @default.
• W1993099545 modified "2023-09-24" @default.
• W1993099545 title "Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access" @default.
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• W1993099545 doi "https://doi.org/10.1109/micro.2012.11" @default.
• W1993099545 hasPublicationYear "2012" @default.
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