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- W1993679085 abstract "The transistor arrangement optimization is an effective possibility to improve VLSI design, especially when generating CMOS logic gates to be inserted in standard cell libraries. This paper addresses this issue and presents a new methodology to generate efficient transistor networks. Starting from an input ISOP, the proposed method is capable to deliver series-parallel and non-series-parallel arrangements with reduced transistor count. By applying the proposed approach, it is possible to achieve optimized transistor arrangements since greedy choices are avoided during part of the generation process. The performed experiments have demonstrated the efficiency of this methodology when comparing to other available techniques." @default.
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- W1993679085 date "2013-05-02" @default.
- W1993679085 modified "2023-09-27" @default.
- W1993679085 title "Efficient transistor-level design of CMOS gates" @default.
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- W1993679085 doi "https://doi.org/10.1145/2483028.2483089" @default.
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