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- W1993989849 abstract "In this paper we propose two synthesizable 3D network architectures: C-LIN and D-LIN, which allow modular stacking of multiple L1 memory dies over a multi-core cluster with a limited number of processing elements (PEs). Two Through Silicon Via (TSV) technologies are used: the state of the art Micro-bumps and the promising and dense Cu-Cu Direct Bonding, with consideration of the ESD protection circuits. Our results demonstrate that, in processor-to-L1-memory context, C-LIN and D-LIN perform significantly better than traditional network on chips and simple time-division multiplexing buses, and they achieve comparable speed vs. their 2D counterparts, while enabling modularity: from 256KB to 2MB L1 memory configurations with a single mask set." @default.
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- W1993989849 date "2013-04-01" @default.
- W1993989849 modified "2023-09-27" @default.
- W1993989849 title "3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters" @default.
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- W1993989849 doi "https://doi.org/10.1109/nocs.2013.6558394" @default.
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