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- W1994557402 abstract "This paper presents a technique for simulating processors and attached hardware using the principle of compiled simulation. Unlike existing, inhouse and off-the-shelf hardware/software co-simulators, which use interpretive processor simulation, the proposed technique performs instruction decoding and simulation scheduling at compile time. The technique offers up to three orders of magnitude faster simulation. The high speed allows the user to explore algorithms and hardware/software trade-offs before any hardware implementation. In this paper, the sources of the speedup and the limitations of the technique are analyzed and the realization of the simulation compiler is presented." @default.
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- W1994557402 date "1996-01-01" @default.
- W1994557402 modified "2023-10-01" @default.
- W1994557402 title "Compiled HW/SW co-simulation" @default.
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- W1994557402 doi "https://doi.org/10.1145/240518.240649" @default.
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