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• W1994898876 abstract "Peak power reduction has been a critical challenge in the design of integrated circuits impacting the chip's performance and reliability. The reduction of peak power also reduces the power density of integrated circuits. Due to large IR-voltage drops in circuits, transistor switching slows down giving rise to timing violations and logic failures. In this paper, we present a new clock control strategy for peak-power reduction in VLSI circuits. In the proposed method, the simultaneous switching of combinational paths is minimized by taking advantage of the delay slacks among the paths and clustering the paths with similar slack values. Once the paths are identified based on the path delays and their slack values, the clustering algorithm determines the ideal number of clusters for the given circuit and for each cluster the maximum possible phase shift that can be applied to the clock. The paths are assigned to clusters in a load balanced manner based on the slack values and each cluster will have a phase shift possible on its clock depending on the slack. Thus, the proposed register-transfer level (RTL) method takes advantage of the logic-path timing slack to re-schedule circuit activities at optimal intervals within the unaltered clock period. When switching activities are redistributed more evenly across the clock period, the IC supply-current consumption is also spread across a wider range of time within the clock period. This has the beneficial effect of reducing peak-current draw in addition to reducing RMS power draw without having to change the operating frequency and without utilizing additional power supply voltages as in dual or multi VT approaches. The proposed method is implemented and tested through simulations using an experimental setup with Synopsys Tools Suite and Cadence Tools on the ISCAS'85 benchmark circuits, OpenCore circuits and LEON processor multiplier circuit. Experimental results indicate that peak power can be reduced significantly to at least 72% depending on the number of clusters and the phase-shifted clock identified as suitable for the given circuit by the proposed algorithms. Although the proposed method incurs some power overhead compared to the traditional clocking method, the overhead can be made negligible compared to the peak-power reduction as seen in the experimental results presented." @default.
• W1994898876 created "2016-06-24" @default.
• W1994898876 creator A5007788756 @default.
• W1994898876 creator A5027665366 @default.
• W1994898876 creator A5047033740 @default.
• W1994898876 creator A5091330162 @default.
• W1994898876 date "2013-02-01" @default.
• W1994898876 modified "2023-09-27" @default.
• W1994898876 title "A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering" @default.
• W1994898876 cites W1971639510 @default.
• W1994898876 cites W1988123824 @default.
• W1994898876 cites W1999640823 @default.
• W1994898876 cites W2004812650 @default.
• W1994898876 cites W2008689571 @default.
• W1994898876 cites W2011579672 @default.
• W1994898876 cites W2039731046 @default.
• W1994898876 cites W2044963234 @default.
• W1994898876 cites W2051230585 @default.
• W1994898876 cites W2068447851 @default.
• W1994898876 cites W2070316659 @default.
• W1994898876 cites W2102627413 @default.
• W1994898876 cites W2103263103 @default.
• W1994898876 cites W2104253428 @default.
• W1994898876 cites W2108904252 @default.
• W1994898876 cites W2110722301 @default.
• W1994898876 cites W2117378467 @default.
• W1994898876 cites W2120463846 @default.
• W1994898876 cites W2123611365 @default.
• W1994898876 cites W2125095037 @default.
• W1994898876 cites W2135347849 @default.
• W1994898876 cites W2144232914 @default.
• W1994898876 cites W2145458400 @default.
• W1994898876 cites W2155755017 @default.
• W1994898876 cites W2156992164 @default.
• W1994898876 cites W2165867688 @default.
• W1994898876 cites W2168322670 @default.
• W1994898876 cites W2169281837 @default.
• W1994898876 cites W2169691372 @default.
• W1994898876 cites W2210982994 @default.
• W1994898876 cites W604599845 @default.
• W1994898876 cites W1924077319 @default.
• W1994898876 doi "https://doi.org/10.1109/tvlsi.2012.2186989" @default.
• W1994898876 hasPublicationYear "2013" @default.
• W1994898876 type Work @default.
• W1994898876 sameAs 1994898876 @default.
• W1994898876 citedByCount "13" @default.
• W1994898876 countsByYear W19948988762013 @default.
• W1994898876 countsByYear W19948988762014 @default.
• W1994898876 countsByYear W19948988762015 @default.
• W1994898876 countsByYear W19948988762016 @default.
• W1994898876 countsByYear W19948988762018 @default.
• W1994898876 crossrefType "journal-article" @default.
• W1994898876 hasAuthorship W1994898876A5007788756 @default.
• W1994898876 hasAuthorship W1994898876A5027665366 @default.
• W1994898876 hasAuthorship W1994898876A5047033740 @default.
• W1994898876 hasAuthorship W1994898876A5091330162 @default.
• W1994898876 hasConcept C111335779 @default.
• W1994898876 hasConcept C115874739 @default.
• W1994898876 hasConcept C119599485 @default.
• W1994898876 hasConcept C119857082 @default.
• W1994898876 hasConcept C125576049 @default.
• W1994898876 hasConcept C127413603 @default.
• W1994898876 hasConcept C134146338 @default.
• W1994898876 hasConcept C137059387 @default.
• W1994898876 hasConcept C14580979 @default.
• W1994898876 hasConcept C165801399 @default.
• W1994898876 hasConcept C172385210 @default.
• W1994898876 hasConcept C174086752 @default.
• W1994898876 hasConcept C201995342 @default.
• W1994898876 hasConcept C22716491 @default.
• W1994898876 hasConcept C24326235 @default.
• W1994898876 hasConcept C2524010 @default.
• W1994898876 hasConcept C33923547 @default.
• W1994898876 hasConcept C41008148 @default.
• W1994898876 hasConcept C60501442 @default.
• W1994898876 hasConcept C73555534 @default.
• W1994898876 hasConcept C90806461 @default.
• W1994898876 hasConcept C93682380 @default.
• W1994898876 hasConceptScore W1994898876C111335779 @default.
• W1994898876 hasConceptScore W1994898876C115874739 @default.
• W1994898876 hasConceptScore W1994898876C119599485 @default.
• W1994898876 hasConceptScore W1994898876C119857082 @default.
• W1994898876 hasConceptScore W1994898876C125576049 @default.
• W1994898876 hasConceptScore W1994898876C127413603 @default.
• W1994898876 hasConceptScore W1994898876C134146338 @default.
• W1994898876 hasConceptScore W1994898876C137059387 @default.
• W1994898876 hasConceptScore W1994898876C14580979 @default.
• W1994898876 hasConceptScore W1994898876C165801399 @default.
• W1994898876 hasConceptScore W1994898876C172385210 @default.
• W1994898876 hasConceptScore W1994898876C174086752 @default.
• W1994898876 hasConceptScore W1994898876C201995342 @default.
• W1994898876 hasConceptScore W1994898876C22716491 @default.
• W1994898876 hasConceptScore W1994898876C24326235 @default.
• W1994898876 hasConceptScore W1994898876C2524010 @default.
• W1994898876 hasConceptScore W1994898876C33923547 @default.
• W1994898876 hasConceptScore W1994898876C41008148 @default.
• W1994898876 hasConceptScore W1994898876C60501442 @default.
• W1994898876 hasConceptScore W1994898876C73555534 @default.
• W1994898876 hasConceptScore W1994898876C90806461 @default.
• W1994898876 hasConceptScore W1994898876C93682380 @default.

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