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- W1995254005 abstract "Coupling capacitance between adjacent wires in on-chip interconnect significantly increases the average transition energy dissipation, and the maximum delay. This paper proposed a novel encoding scheme to, further, reduce the coupling energy dissipation, and delay. Specifically for 65nm CMOS technology, we present an 8-bit to 10-bit equivalent solution that reduces the energy dissipation by 55%, and delay by 24%, without any additional area penalty, while requiring a less complex circuit overhead when compared with transition pattern coding (TPC) scheme." @default.
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- W1995254005 date "2009-01-01" @default.
- W1995254005 modified "2023-10-01" @default.
- W1995254005 title "An optimization strategy for low energy and high performance for the on-chip interconnect signalling" @default.
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- W1995254005 doi "https://doi.org/10.1145/1594233.1594304" @default.
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