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- W1996143952 abstract "A recent trend in the research of ROM-less DDFS architecture, which is endowed with high speed, low power and high SFDR features and will generate the sine or cosine waveforms within a broad frequency range. In this work one high-speed, low-power, and low-latency pipelined ROM-less DDFS has been proposed and implemented in Xilinx Virtex-II Pro FPGA. The proposed ROM-less DDFS design has 32 bit phase input and 16 bit amplitude resolution with maximum amplitude error of 1.5×10−4. The FPGA implementation of the proposed design has an SFDR of −94.3 dBc and maximum operation frequency of 276 MHz by consuming only 22 K gate and 1.05 mW/MHz power. The high speed of operation and low power makes the propose design suitable for the use in communication transceiver for the up and down conversion." @default.
- W1996143952 created "2016-06-24" @default.
- W1996143952 creator A5003667123 @default.
- W1996143952 creator A5082686709 @default.
- W1996143952 date "2010-10-01" @default.
- W1996143952 modified "2023-09-26" @default.
- W1996143952 title "A high-speed, ROM-less DDFS for software defined radio system" @default.
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- W1996143952 doi "https://doi.org/10.1109/icccct.2010.5670538" @default.
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