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- W1996770195 abstract "NAND Flash memory is widely used in recent SoCs. High density NAND Flash requires Error Correcting Code (ECC) mechanism to guarantee data integrity. We propose an efficient ECC model which decrease multi bit errors by considering the Flash memory's characteristic. According to the Flash memory mechanism, 0's error is more likely to happen than 1's error. The proposed error control code counts the number of `1' in a word and inverts all bits to keep the number of 1 is more than that of 0s, which signify a high quantity of Hamming weight. We confirm that the proposed method is not only effective for single error but also dramatically effective for multi bit error." @default.
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- W1996770195 date "2010-10-01" @default.
- W1996770195 modified "2023-10-16" @default.
- W1996770195 title "Error rate decrease through Hamming weight change for NAND Flash" @default.
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- W1996770195 doi "https://doi.org/10.1109/iscit.2010.5665147" @default.
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