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• W1997411420 abstract "We present a power estimation technique for digital integrated circuits that operates at the register transfer level (RTL). Such a high-level power estimation capability Is required in order to provide early warning of any power problems before the circuit-level design has been specified. With such early warning, the designer can explore design trade-offs at a higher level of abstraction than previously possible, reducing design time and cost. Our estimator is based on the use of entropy as a measure of the average activity to be expected in the final implementation of a circuit, given only its Boolean functional description. This technique has been implemented and tested on a variety of circuits. The empirical results to be presented are very promising and demonstrate the feasibility and utility of this approach." @default.
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• W1997411420 date "1996-06-01" @default.
• W1997411420 modified "2023-10-01" @default.
• W1997411420 title "Towards a high-level power estimation capability [digital ICs]" @default.
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• W1997411420 doi "https://doi.org/10.1109/43.503929" @default.
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