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- W1997681036 abstract "Submicron CMOS process technologies for a high density 4M DRAM are presented emphasizing a cell area reduction to 10.9 um2 using a newly proposed FASIC cell. Two novel techniques were developed to realize the new cell structure. The oblique ion implantation technique can make a shallow impurity doping into the side wall and the local oxidation at the side wall technique makes the half-contact/cell architecture on the peripheral trench type cell." @default.
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- W1997681036 date "1986-01-01" @default.
- W1997681036 modified "2023-09-23" @default.
- W1997681036 title "A high density 4M DRAM process using folded bitline adaptive side-wall isolated capacitor (FASIC) cell" @default.
- W1997681036 doi "https://doi.org/10.1109/iedm.1986.191134" @default.
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