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• W1997965829 abstract "Circuit switching activity during scan test is high and results in high average and instantaneous power consumption, which is becoming a concern for scan-based architecture. This paper presents a novel low power compression architecture for scan testing. A low power feedback MUX is added to the scan chains structure. Also, this paper maps the sequential test planning problems to a combinational circuit which can deal with arbitrary at-speed delay-test clock schemes." @default.
• W1997965829 created "2016-06-24" @default.
• W1997965829 creator A5030921116 @default.
• W1997965829 creator A5032764121 @default.
• W1997965829 date "2012-10-01" @default.
• W1997965829 modified "2023-09-25" @default.
• W1997965829 title "A revised low power test architecture" @default.
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• W1997965829 doi "https://doi.org/10.1109/iscit.2012.6380894" @default.
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