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Matches in SemOpenAlex for { <https://semopenalex.org/work/W1998161811> ?p ?o ?g. }

• W1998161811 abstract "A 3D packaging technology has been developed for 4 Gbit DRAM. Highly-doped poly-Si through-silicon vias (TSVs) are used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM compatible process. Through optimization of the process conditions and layout design, fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using the so-called SMAFTI technology. A new bump and wiring structure for feedthrough interposer (FTI) has also been developed for fine-pitch and low-cost bonding. Simulation of the transfer function of FTI wiring indicated a 3 Gbps/pin data transfer capability" @default.
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• W1998161811 date "2006-01-01" @default.
• W1998161811 modified "2023-10-01" @default.
• W1998161811 title "A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer" @default.
• W1998161811 cites W3146109873 @default.
• W1998161811 doi "https://doi.org/10.1109/iedm.2006.346849" @default.
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