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- W1998461180 abstract "We describe the design and VHDL implementation of a cache coherent MPSoC named minimalist cache coherent MPSoC (MCCM). The system comprises one to eight MIPS-I processors, coherent primary data caches, memory management units, memory controller and the interconnection. We present a detailed account of the implementation, focusing on the shared memory subsystem. A simple benchmark is used to assess the overall system functionality. We compared the size of our design to that of a LEON3-based multiprocessor and found that a four-core LEON3 system needs roughly the same amount of logic/state as a six to eight cores MCCM." @default.
- W1998461180 created "2016-06-24" @default.
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- W1998461180 date "2011-01-01" @default.
- W1998461180 modified "2023-09-27" @default.
- W1998461180 title "A minimalist cache coherent MPSoC designed for FPGAs" @default.
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- W1998461180 doi "https://doi.org/10.1504/ijhpsa.2011.040460" @default.
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