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- W1999235248 abstract "A 2.4-GHz low-noise sub-harmonic direct-conversion receiver (SH-DCR) is demonstrated using standard 0.18- <formula formulatype=inline xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex Notation=TeX>$mu$</tex> </formula> m CMOS technology. Deep-n-well vertical-NPN (V-NPN) bipolar junction transistors (BJTs) are employed to solve the flicker noise problem in CMOS process. Design optimization of a power-constrained noise-impedance-matched low-noise amplifier (LNA) with the effect of lossy on-chip inductors is fully discussed in this paper. A multi-stage octet-phase polyphase filter is analyzed in detail and implemented to generate well balanced octet-phase LO signals. As a result, the demonstrated receiver achieves 51-dB voltage gain and 3-dB noise figure with flicker noise corner less than 30 kHz when <formula formulatype=inline xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> <tex Notation=TeX>${rm RF} = 2.4$</tex></formula> GHz. The I/Q amplitude/phase mismatch is below <formula formulatype=inline xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex Notation=TeX>${pm}0.2$</tex> </formula> dB/ <formula formulatype=inline xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink><tex Notation=TeX>${pm}1^{circ}$</tex> </formula> , respectively, covering from 2.35 to 2.6 GHz. The dc current consumption is 5 mA at a 1.8-V supply." @default.
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- W1999235248 date "2013-02-01" @default.
- W1999235248 modified "2023-10-16" @default.
- W1999235248 title "A 2.4-GHz Low-Flicker-Noise CMOS Sub-Harmonic Receiver" @default.
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- W1999235248 doi "https://doi.org/10.1109/tcsi.2012.2215794" @default.
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