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• W2000147479 abstract "Implementing serial I/O receivers based on analog-to-digital converters (ADCs) and digital signal post-processing has drawn growing interest with technology scaling, but power consumption remains among the key issues for such digital receiver in high speed applications. This paper presents an ADC-based receiver that uses a low-gain analog and mixed-mode pre-equalizer in conjunction with non-uniform reference levels for the ADC. The combination compensates for both the frontend non-ideality and the channel response while maintaining low ADC resolution and hence enables low power consumption. The receiver is fabricated in a 65 nm CMOS technology with 10 Gb/s data rate, and has 13 pJ/bit and 10.6 pJ/bit power efficiency for a 29 dB and a 23 dB loss channel respectively." @default.
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• W2000147479 date "2012-04-01" @default.
• W2000147479 modified "2023-09-27" @default.
• W2000147479 title "Power Optimized ADC-Based Serial Link Receiver" @default.
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• W2000147479 doi "https://doi.org/10.1109/jssc.2012.2185356" @default.
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