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- W2000206596 abstract "We implemented a low-voltage latch circuit topology in a full-rate 4:1 multiplexer (MUX) using InP-HBT technology. The proposed latch circuitry incorporates parallel current switching together with inductive peaking a combination that makes it suitable for over-40-Gb/s operation at supply voltages ranging from 1.5 to 1.8 V. The full-rate 4:1 MUX provided 40-Gb/s error-free operation with a power dissipation of only 1 W at a supply voltage of 1.8 V. The D-flip/flop (D-F/F) based on this latch circuitry provided 50-Gb/s D-F/F operation at a supply voltage as low as 1.5 V. Demultiplexing operation was also confirmed for the D-F/F with this circuit technology at a data rate of up to 110Gb/s with a 1.8-V supply voltage. The latch circuitry should help enable development of a low-voltage 40-Gb/s full-rate module which can be seamlessly connected with high-speed CMOS I/O circuits." @default.
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- W2000206596 date "2005-10-01" @default.
- W2000206596 modified "2023-09-27" @default.
- W2000206596 title "Low supply voltage operation of over-40-Gb/s digital ICs based on parallel-current-switching latch circuitry" @default.
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- W2000206596 doi "https://doi.org/10.1109/jssc.2005.854593" @default.
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