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- W2000267092 abstract "Traditional dynamic simulation with standard delay format (SDF) back-annotation cannot be reliably performed on large designs. The large size of SDF files makes the event-driven timing simulation extremely slow as it has to process an excessive number of events. In order to accelerate gate-level timing simulation we propose an automated fast prediction-based gate-level timing simulation that combines static timing analysis (STA) at the block level with dynamic timing simulation at the I/O interfaces. We demonstrate that the proposed timing simulation can be done earlier in the design cycle in parallel with synthesis." @default.
- W2000267092 created "2016-06-24" @default.
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- W2000267092 date "2014-03-24" @default.
- W2000267092 modified "2023-09-24" @default.
- W2000267092 title "Fast STA prediction-based gate-level timing simulation" @default.
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- W2000267092 doi "https://doi.org/10.5555/2616606.2616977" @default.
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